View MPC5602DPB_1160047.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

freescale semiconductor product brief document number: MPC5602DPB rev. 3.1, 02/2011 contents ? freescale semiconductor, inc., 2010. all rights reserved. preliminary?subject to change without notice the 32-bit mpc5602d automo tive microcontrollers are a family of system-on-chip (soc) devices designed to be central to the development of the next wave of central vehicle body controller, smart junction box, front module, peripheral body, door control and seat control applications. the mpc5602d family is one of a series of next-generation automotive microcontrollers based on the power architecture ? technology and designed specifically for embedded applications. this document describes the features of the device and options available within the family members, and highlights important el ectrical and physical characteristics of the device. mpc5602d microcontroller product brief 1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1.1 mpc5602d features . . . . . . . . . . . . . . . . . . . . . . . . 2 2 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 device family overview . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3.1 mpc5602d family comparison . . . . . . . . . . . . . . . . 6 3.2 critical performance parameters . . . . . . . . . . . . . . . 7 3.3 low power operation . . . . . . . . . . . . . . . . . . . . . . . 10 3.4 chip-level features. . . . . . . . . . . . . . . . . . . . . . . . . 11 3.5 module features. . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.6 packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4 application example . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.1 body controller application example . . . . . . . . . . . 24 5 developer environment . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6 orderable parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7 revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
mpc5602d microcontroller product brief, rev. 3.1 preliminary?subject to change without notice introduction freescale semiconductor 2 1 introduction the device core capitalizes on the available development infrastructu re of current po wer architecture devices and is supported with softwa re drivers, operating systems and c onfiguration code to assist with users? implementations. refer to section 5, ?developer environment for more information. table 2 provides specific memory and feature sets of the roadmap product members. the advanced and cost-efficient host pr ocessor core of this automotive c ontroller family complies with the power architecture ? technology. it operates at speeds of up to 48 mhz and offers high performance processing optimized for low power consumption. the device platform has a si ngle level of memory hierarchy and can support a wide range of on-chip static random access memory (sram) and internal flash memory. 1.1 mpc5602d features ? single issue, 32-bit cp u core complex (e200z0h) ? compliant with the power architecture ? embedded category ? includes an instruction set e nhancement allowing variable lengt h encoding (vle) for code size footprint reduction. with the optional encoding of mixed 16-bit and 32-bit instructions, it is possible to achieve significant code size footprint reduction. ? up to 256 kb on-chip code flash su pported with flash controller and ecc ? 64 kb on-chip data flash with ecc ? up to 16 kb on-chip sram with ecc ? interrupt controller (intc) with multiple interrupt vectors, incl uding 20 external interrupt sources and 18 external interrupt/wakeup sources ? frequency modulated phase-locked loop (fmpll) ? crossbar switch architecture for concurrent acces s to peripherals, flash, or sram from multiple bus masters ? boot assist module (bam) suppor ts internal flash programming vi a a serial link (can or sci) ? timer supports input/output cha nnels providing a range of 16-bit input capture, output compare, and pulse width modulatio n functions (emios-lite) ? up to 33 channel 12-bit analog-to-digital converter (adc) ? 2 serial peripheral interface (dspi) modules ? 3 serial communication interface (linflex) modules ? 1 enhanced full can (flexcan) module with configurable buffers ? up to 79 configurable gene ral purpose pins supporting input and output operations (package dependent) ? real time counter (rtc) with clock source fr om 128 khz or 16 mhz internal rc oscillator supporting autonomous wakeup with 1 ms re solution with max timeout of 2 seconds ? up to 4 periodic interru pt timers (pit) with 32-bit counter resolution ? 1 system module timer (stm)
introduction mpc5602d microcontroller product brief, rev. 3.1 preliminary?subject to change without notice freescale semiconductor 3 ? nexus development interface (ndi) per ieee-isto 5001-2003 class 1 standard ? device/board boundary scan testing supported with per joint test action group (j tag) of ieee (ieee 1149.1) ? on-chip voltage regulator (vreg) for regula tion of input supply for all internal levels
mpc5602d microcontroller product brief, rev. 3.1 preliminary?subject to change without notice block diagram freescale semiconductor 4 2 block diagram figure 1 shows a top-level block diag ram of the mpc5602d family. table 1 provides furthe r details on the block functions. figure 1. mpc5602d series block diagram 2 x dspi fmpll nexus 1 sram siul reset control 16 kb external imux gpio & jtag pad control jtag port e200z0h interrupt requests 64-bit 3 x 3 crossbar switch 1 x flexcan peripheral bridge interrupt request interrupt request i/o clocks instructions data voltage regulator nmi swt pit stm nmi siul . . . . . . . . . . . . intc 3 x linflex 1 x emios 33 ch. adc cmu sram flash code flash 256 kb data flash 64 kb mc_pcu mc_me mc_cgm mc_rgm bam ctu rtc sscm (master) (master) (slave) (slave) (slave) controller controller legend: adc analog-to-digital converter bam boot assist module cmu clock monitor unit ctu cross triggering unit dspi deserial serial peripheral interface ecsm error correction status module edma enhanced direct memory access emios enhanced modular input output system flash flash memory flexcan controller area network (flexcan) fmpll frequency-modulated phase-locked loop imux internal multiplexer intc interrupt controller jtag jtag controller linflex serial communication interface (lin support) mc_cgm clock generation module mc_me mode entry module mc_pcu power control unit mc_rgm reset generation module nmi non-maskable interrupt pit periodic interrupt timer rtc real-time clock siul system integration unit lite sram static random-access memory sscm system status configuration module stm system timer module swt software watchdog timer wkpu wakeup unit xbar crossbar switch edma ecsm from peripheral blocks wkpu request interrupt request (master)
block diagram mpc5602d microcontroller product brief, rev. 3.1 preliminary?subject to change without notice freescale semiconductor 5 table 1. mpc5602d series block summary block function analog-to-digital converter (adc) multi-channel, 12-bit analog-to digital-converter boot assist module (bam) a block of read-only memory containing vle code which is executed according to the boot mode of the device clock generation module (mc_cgm) provides logic and contro l required for the generatio n of system and peripheral clocks clock monitor unit (cmu) monitors clock source (internal and external) integrity cross triggering unit (ctu) enables synchronization of adc conversions with a timer event from the emios or from the pit crossbar switch (xbar) supports si multaneous connections between two master po rts and three slave ports. the crossbar supports a 32-bit address bus width and a 64-bit data bus width. deserial serial peripheral interface (dspi) provides a synchronous serial interface for communication with external devices enhanced direct memory access (edma) performs complex data transfers with minimal intervention from a host processor via ? n ? programmable channels. enhanced modular input output system (emios) provides the functionality to generate or measure events error correction status module (ecsm) provides a myriad of miscellaneous control functions for the device including program-visible information about configurat ion and revision levels, a reset status register, wakeup control for exiting sleep modes, and optional features such as information on memory errors re ported by error-correcting codes flash memory provides non-volatile storage for program code, constants and variables flexcan (controller area network) supports the standard can communications protocol frequency-modulated phase-locked loop (fmpll) generates high-speed system clocks and supports programmable frequency modulation internal multiplexer (imux) siu subblock allows flexible mapping of peripheral interface on the different pins of the device interrupt controller (intc) provides priority-based preemptive scheduling of interrupt requests jtag controller provides the means to test chip functionality and connectivity while remaining transparent to syst em logic when not in test mode linflex controller manages a high number of lin (local interconnect network protocol) messages efficiently with a minimum of cpu load mode entry module (mc_me) provides a mechanism for controlling the device operational mode and mode transition sequences in all functional st ates; also manages the power control unit, reset generation module and clock generation module, and holds the configuration, control and status registers accessible for applications non-maskable interrupt (nmi) handles external events t hat must produce an immediate response, such as power down detection periodic interrupt timer (pit) produces periodic interrupts and triggers power control unit (mc_pcu) reduces the overall power consumption by disconnecting parts of the device from the power supply via a power switching device; device components are grouped into sections called ?power domains? which are controlled by the pcu
mpc5602d microcontroller product brief, rev. 3.1 preliminary?subject to change without notice device family overview freescale semiconductor 6 3 device family overview this section provides a comparison of the different mpc5602d family members, presents the critical performance parameters, and lists bo th the chip-level and module feat ures as well as the available packages. 3.1 mpc5602d family comparison table 2 provides a summary of the different member s of the mpc5602d family and their proposed features. this information is intended to provide an understanding of the range of func tionality offered by this family. real-time counter (rtc) provides a free-running counte r and interrupt generation capability that can be used for timekeeping applications reset generation module (mc_rgm) centralizes reset sources and manages the device reset sequence of the device static random-access memory (sram) provides storage for program code, constants, and variables system integration unit lite (siul) provides control over all the electrical pad controls and up 32 ports with 16 bits of bidirectional, general-purpose input and output signals and supports up to 32 external interrupts with trigger event configuration system status and configuration module (sscm) provides system configurati on and status data (such as memory size and status, device mode and security status), device identification data, debug status port enable and selection, and bus and peripheral abort enable/disable system timer module (stm) provides a set of output compare events to support autosar and operating system tasks system watchdog timer (swt) provides protection from runaway code wakeup unit (wkpu) supports up to 18 external sources that can generate interrupts or wakeup events, of which 1 can cause non-maskable interrupt requests or wakeup events. table 2. mpc5602d device comparison feature device mpc5601dxlh mpc5601dxll mpc5602dxlh mpc5602dxll cpu e200z0 execution speed static ? up to 48 mhz code flash 128 kb 256 kb data flash 64 kb (4 16 kb) sram 12 kb 16 kb edma 16 ch table 1. mpc5602d series block summary (continued) block function
device family overview mpc5602d microcontroller product brief, rev. 3.1 preliminary?subject to change without notice freescale semiconductor 7 3.2 critical performance parameters the critical performance parameters of the mpc5602d feature the following: ? fully static design operation up to a maximum of 48 mhz, based on 125 ? c ambient temperature ? low power design ? designed for dynamic power manage ment of core and peripherals ? software-controlled cloc k gating of peripherals ? multiple power domains to minimi ze leakage in low power modes ? internal voltage regulator (vreg) enables control with a single i nput voltage for device operation below 100 ma with optional external ballast resistor for supporti ng maximum performance ? 3.3 or 5 v 10% input supply voltage ? adc analog supply 3.3 or 5 v 10% ? configurable pins ? selectable pull-up, pull-down, or no pull on all gpio pins ? selectable open-drain pin adc 16 ch, 12-bit 33 ch, 12-bit 16 ch, 12-bit 33 ch, 12-bit ctu 16 ch total timer i/o 1 emios 13 ch, 16-bit 28 ch, 16-bit 13 ch, 16-bit 28 ch, 16-bit ? type x 2 2ch 5ch 2ch 5ch ? type y 3 ?9ch?9ch ? type g 4 7ch 7ch 7ch 7ch ? type h 5 4ch 7ch 4ch 7ch sci (linflex) 3 spi (dspi) 2 can (flexcan) 1 gpio 6 45 79 45 79 debug jtag package 64 lqfp 100 lqfp 64 lqfp 100 lqfp notes: 1 refer to emios section of device reference manual for information on the channel configuration and functions. 2 type x = mc + mcb + opwmt + opwmb + opwfmb + saic + saoc 3 type y = opwmt + opwmb + saic + saoc 4 type g = mcb + ipwm + ipm + daoc + opwmt + opwmb + opwfmb + opwmcb + saic + saoc 5 type h = ipwm + ipm + daoc + opwmt + opwmb + saic + saoc 6 i/o count based on multiplexing with peripherals table 2. mpc5602d device comparison (continued) feature device mpc5601dxlh mpc5601dxll mpc5602dxlh mpc5602dxll
mpc5602d microcontroller product brief, rev. 3.1 preliminary?subject to change without notice device family overview freescale semiconductor 8 ? frequency modulated phase-locked loop ? -40 to 125 c ambient operating temperature range 1 1. assuming that the absolute maximum of 150 c junction temperature is respected table 3. operating mode summary 1 notes: 1 ta bl e ke y : apd: analog power-down bam: boot assist module software and hardware used for device startup and configuration cg: clock gated, powered but clock stopped fp: vreg full performance mode lp: vreg low power mode, reduced output ca pability of vreg but lower power consumption off: powered off and clock gated on: powered and clocked op: optionally configurable to be enabled or disabled (clock gated) por: power-on reset var: variable duration, based on the required re configuration and execution clock speed configuration operating modes soc features clock sources periodic wakeup wakeup input vreg mode wakeup time 2 2 a high level summary of some key durations that need to be considered when recovering from low power modes. this does not account for all durations at wakeup. other delays will be necessary to consider including, but not limited to the external supply startup time. irc wakeup time must not be added to the overall wak eup time as it starts in parallel with the vreg. all other wakeup times must be added to determine the total startup time. for example, out of standby, if flash is needed, the total wakeup time will be 120 s. core peripherals flash sram pll 16 mhz irc x osc 128 khz irc vreg startup irc wakeup flash recovery osc stabilization pll lock s/w reconfig mode switch over run on op op on op on op on ? ? fp ? ? ? ? ? ? ? halt cg op op on op on op on op op fp ? ? ? ? ? ? tbd 3 3 tbd: to be defined stop cg op apd on cg op op on op op lp 25 s 8 s >125 s 8 ms 200 s ? 33 s standby off off off 16 kb 4 4 16 kb of sram content retained but not accessible in standby mode off op off op op op lp 25 s 8 s >125 s 8 ms 200 s var 33 s por ? ? ? ? ? ? ? ? ? ? ? 250 s 8 s >125 s 8 ms 200 s ? bam
device family overview mpc5602d microcontroller product brief, rev. 3.1 preliminary?subject to change without notice freescale semiconductor 9 table 4. i/o characteristics, v dde = 5.0 v 1 notes: 1 please refer to the data sheet for up-to-date valu es on current consumption. the values presented in this table are only estimates and have not been validated. parameter symbol value 2 2 tbd: to be defined equation input voltage high v ih 3.575 v v dde ?? 0.65 input voltage low v il 1.925 v v dde ?? 0.35 output voltage high v oh 4.4 v v dde ?? 0.8 output voltage low v ol 1.1 v v dde ?? 0.2 output drive strength (slow pads) 3 3 refer to device data sheet for details of whic h pins are implemented with slow pads and pin conditions. i drv_s 2 ma ? output drive strength (medium pads) 4 4 refer to device data sheet for details of whic h pins are implemented wit h medium pads and pin conditions. i drv_m 2 ma ? i/o dc injection current 5 5 max per pin injection current that will not corrupt ad jacent pins. maximum injection current must not exceed 25 ma for complete device. i ic tbd ? total maximum i/o current i io 65 ma ? table 5. i/o characteristics, v dde = 3.3 v 1 notes: 1 please refer to the data sheet for up-to-date valu es on current consumption. the values presented in this table are only estimates and have not been validated. parameter symbol value 2 2 tbd: to be defined equation input voltage high v ih 2.145 v v dde ?? 0.65 input voltage low v il 1.155 v v dde ?? 0.35 output voltage high v oh 3.64 v v dde ?? 0.8 output voltage low v ol 0.66 v v dde ?? 0.2 output drive strength (slow pads) 3 3 refer to device data sheet for details of whic h pins are implemented with slow pads and pin conditions. i drv_s 1 ma ? output drive strength (medium pads) 4 4 refer to device data sheet for details of whic h pins are implemented wit h medium pads and pin conditions. i drv_m 1 ma ? i/o dc injection current 5 5 max per pin injection current that will not corrupt ad jacent pins. maximum injection current must not exceed 25 ma for complete device. i ic tbd ? total maximum i/o current i io 65 ma ?
mpc5602d microcontroller product brief, rev. 3.1 preliminary?subject to change without notice device family overview freescale semiconductor 10 3.3 low power operation mpc5602d devices provide two dyna mic power modes?run and halt ?and two static low power modes?standby and stop. both low power modes use clock gating to halt the clock for all or part of the device. additionally, the standby mode uses power gating to automatically turn off the power s upply to parts of the device to minimize leakage. run modes are the main operating modes where the en tire device can be powered and clocked. four dynamic run modes are supported?run0 - run3. the ability to confi gure and select different run modes enables different clocks and pow er configurations to be supported with respect to each other and to allow switching between different operating conditions. the necessary pe ripherals, clock sources, clock speed and systems clock prescalers can be independen tly configured for each of the four run modes of the device. halt mode is a reduced activity, low power mode intended for modera te periods of lower processing activity. in this mode the core sy stem clocks are stopped but user-selec ted peripheral tasks can continue to run. it can be configured to provi de more efficient power management features (switch-off pll, flash memory, main regulator, etc.) at the cost of longer wake up latency. the system returns to run mode as soon as an event or interrupt is pending. stop mode maintains power to the entire device al lowing the retention of al l on-chip registers and memory, and providing a faster rec overy low power mode than the lo west standby mode. there is no need to reconfigure the de vice before executing code. the clocks to the core and peripherals are halted and can be optionally stopped to the oscillator or pll at the expense of a slower start-up time. stop is entered from run mode only. wakeup from st op mode is triggered by an external event or by the internal periodic wakeup, if enabled. table 6. fmpll characteristics 1 notes: 1 please refer to the data sheet for up-to-date valu es on current consumption. the values presented in this table are only estimates and have not been validated. parameter value 2 2 tbd: to be defined reference frequency range 4 mhz ? 16 mhz cpu clock frequency range 0 hz ? 48 mhz pll multipliers tbd pll dividers tbd pll output frequency 16 ? 48 mhz modulation depth 4% modulation frequency tbd pll long term jitter 10 ns pll stabilization time 3 3 typical stabilization time with stable oscillator (f pllin = 16 mhz) <200s
device family overview mpc5602d microcontroller product brief, rev. 3.1 preliminary?subject to change without notice freescale semiconductor 11 standby mode halts the clock to the entire device and turns off the power to the majority of the chip to offer the lowest power consumption mode. the device can be woken up from standby mode by any of up to 18 external wakeup pins, a reset, or from a periodic wakeup using a low pow er oscillator. if required by the us er, it is possible to enable the internal 16 mhz or 128 khz rc oscillator. in standby mode, the contents of the cores, on-chip peripheral registers and potentially some of the volatile memory are not held. stanb dy mode retains 16 kb of the sram a fast wakeup using the on-chip 16 mhz internal rc oscillator allows rapid execution from sram on exit from low power modes. this os cillator supports low speed code ex ecution and clocking of peripherals through selection as the system clock, and it can be us ed as the pll input clock source to provide fast startup without the exte rnal oscillator delay. in low power modes, the internal 16 mhz rc os cillator also supports the operation of adcs. additionally, up to 18 external wakeup pins are availa ble for wakeup, and a fast startup internal voltage regulator provides a rapid exit from low power modes. 3.4 chip-level features on-chip modules available within the fa mily include the fo llowing features: ? single issue, 32-bit cp u core complex (e200z0h) ? compliant with the power architecture embedded category ? includes an instruction set e nhancement allowing variable lengt h encoding (vle) for code size footprint reduction. with the optional encoding of mixed 16-bit and 32-bit instructions, it is possible to achieve significant code size footprint reduction. ? up to 256 kb on-chip code flash supported with the flash controller ? 64 kb on-chip data flash ? up to 16 kb on-chip sram ? interrupt controller (intc) capable of hand ling 155 selectable-priority interrupt sources ? frequency modulated phase-locked loop (fmpll) ? crossbar switch architecture for concurrent acces s to peripherals, flash, or sram from multiple bus masters ? 16-channel edma controller with multiple transfer request sources using dmamux ? boot assist module (bam) suppor ts internal flash programming vi a a serial link (can or sci) ? timer supports input/output cha nnels providing a range of 16-bit input capture, output compare, and pulse width modulatio n functions (emios-lite) ? one 12-bit analog-to-digital converters (adc) ? cross trigger unit (ctu) to enab le synchronization of adc conversions with a timer event from the emios or from the pit ? 2 serial peripheral interface (dspi) modules ? 3 serial communication interface (linflex) modules
mpc5602d microcontroller product brief, rev. 3.1 preliminary?subject to change without notice device family overview freescale semiconductor 12 ? 1 enhanced full can (flexcan) module with configurable buffers ? up to 79 configurable gene ral purpose pins supporting input and output operations (package dependent) ? real-time counter (rtc) ? clock source from internal 128 khz or 16 mhz oscillator s upporting autonomous wakeup with 1 ms resolution with maximum timeout of 2 seconds ? up to 4 periodic interru pt timers (pit) with 32-bit counter resolution ? device/board boundary scan te sting supported per joint test action group (jtag) of ieee (ieee 1149.1) ? on-chip voltage regulator (vreg) for regula tion of input supply for all internal levels 3.5 module features the following sections provide more details of the modules impl emented on the mpc5602d. 3.5.1 e200z0h core processor the e200z0h core includes the following features: ? high performance, low cost e200z0h core pro cessor for managing peripherals and interrupts ? single issue 4-stage pipeli ned in-order execution, 32-bit power architecture cpu ? variable length encoding (vle), allowi ng mixed 16-bit and 32-bit instructions ? results in efficient code size footprint ? minimizes impact on performance ? branch processing acceleration us ing lookahead instruction buffer ? load/store unit ? 1-cycle load latency ? misaligned access support ? no load-to-use pipeline bubbles ? thirty-two 32-bit genera l purpose registers (gprs) ? separate instruction bus and load/store bus harv ard architecture with separate instruction and load/store buses ? hardware vectored interrupt support ? reservation instructions for implem enting read-modify-write constructs ? multi-cycle divide word (divw), and load multiple word (lmw) stor e multiple word (smw) multiple class instructions, can be interrupted to prevent increases in interrupt latency ? nexus1 support
device family overview mpc5602d microcontroller product brief, rev. 3.1 preliminary?subject to change without notice freescale semiconductor 13 3.5.2 crossbar switch (xbar) the following summarizes the mpc5602d?s implementation of the crossbar switch: ? 3 master ports: ? cpu instruction bus ? cpu load/store bus ?edma ? multiple bus slaves to enable access to flash memory, sram and peripherals ? crossbar supports up to 2 consec utive transfers at any one time ? 32-bit internal address bus , 32-bit internal data bus ? fixed priority arbitrat ion based on port master 3.5.3 interrupt controller (intc) the mpc5602d implements an interrupt controller that features the following: ? unique 9-bit vector for each of the 155 separate interrupt sources ? 8 software triggerable interrupt sources ? 16 priority levels with fixed hardware arbitrati on within priority levels for each interrupt source ? ability to modify the isr or task priority ? external high priority interrupt directly accessing the main core critical interrupt mechanism 3.5.4 system integration unit lite (siul) the siul features the following: ? up to 4 levels of internal pin multiplexing, allo wing exceptional flexibility in the allocation of device functions for each package ? centralized general purpose input output (gpio) control of up to 79 input/output pins (package dependent) ? all gpio pins independently configurab le to support pull-up, pull down, or no pull ? reading and writing to gpio supported both as individual pins and 16-bit wide ports ? all peripheral pins can be alte rnatively configured as both gene ral purpose input or output pins except adc channels which suppor t alternative configuration as general purpose inputs, with selected pins able to also support outputs ? direct readback of the pin value supported on all digita l output pins through the siul ? configurable digital input filter that can be appl ied to up to 16 general pur pose input pins for noise elimination on external interrupts ? register configuration protected ag ainst change with soft lock for temporary guard or hard lock to prevent modification until next reset ? support for two 32-bit virtual ports via the dspi serialization
mpc5602d microcontroller product brief, rev. 3.1 preliminary?subject to change without notice device family overview freescale semiconductor 14 3.5.5 flash memory the on-chip flash memory on the mpc5602d features the following: ? up to 256 kbyte code flash ?2 ? 16 kb, 3 ? 32 kb and 1 ? 128 kb sectors ? typical flash-memory access time: 0 wait-state for buffer hits, 2 wait-states for page buffer miss at 48 mhz ? page buffers can be allocated for code-only, fixe d partitions of code a nd data, all available for any access ? 64-bit ecc with single-bit correction, double-bit detection for data integrity ? censorship protection scheme to prev ent flash-memory content visibility ? separate dedicated data flash for eeprom emulation ? 4 erase sectors each containing 16 kb of memory ? offers read-while-write functi onality from main program space ? small block flash-memory arra ngement in main array to suppor t features such as boot block, operating system block ? hardware managed flash memory wr ites, erase and verify sequence ? error correction status ? configurable error-correct ing codes (ecc) reporting for sram and flash memory ? supports optional reporting of single-bit errors ? protected mechanism for repor ting of corrected ecc values ? error address recorded incl uding access type and master ? flash-memory ecc reporting regi sters mirrored into ecsm address space but data comes from the flash-memory module ? flash-memory module can be interrogate d to provide ecc bit error location ? margin read for flash-memory array s upported for initial program verification 3.5.6 sram the on-chip sram on the mpc5602d features the following: ? up to 16 kb general purpose ram ? typical sram access time: 0 wait-s tate for reads and 32-bit writes; 1 wait-state for 8- and 16-bit writes if back to back with a read to same memory block ? 32-bit ecc with single-bit correction, double-bit detection for data integrity ? supports byte (8-bit), half word (16-bit), and wo rd (32-bit) writes for optimal use of memory ? user transparent ecc encoding and decoding for byte, half word, and word accesses
device family overview mpc5602d microcontroller product brief, rev. 3.1 preliminary?subject to change without notice freescale semiconductor 15 3.5.7 boot assist module (bam) the device implements a boot assist module (bam): ? block of read-only memory cont aining vle code which is executed according to boot mode of the device ? download of code into internal sram possible via flexcan or linflex, af ter which code can be executed 3.5.8 enhanced modular input output system (emios) the mpc5602d implements a scaled- down version of the emios module: ? up to 28 timed i/o channels with 16-bit counter resolution ? buffered updates ? support for shifted pwm outputs to mini mize occurrence of concurrent edges ? supports configurable trigger out puts for adc conversion for sync hronization to channel output waveforms ? edge-aligned output pulse width modulation ? programmable pulse pe riod and duty cycle ? supports 0% and 100% duty cycle ? shared or independent time bases ? dma transfer support available table 7 shows the supported emios modes. table 7. supported emios channel modes mode channel type description name counter / opwm / icoc o(i)pwm / opwfmb / opwmcb / icoc o(i)pwm / icoc opwm / icoc double action output compare daoc x x x ? general purpose input / output gpio x x x x input filter ipf x x x x input period measurement ipm x x x ? input pulse width measurement ipwm x x x ? modulus counter mc x ? ? ? modulus counter buffered (up / down) mcb x x ? ? output pulse width and frequency modulation buffered opwfmb x x ? ? output pulse width modulation buffered opwmb ? x x x center aligned output pwm buffered with dead time opwmcb ? x ? ?
mpc5602d microcontroller product brief, rev. 3.1 preliminary?subject to change without notice device family overview freescale semiconductor 16 table 8 shows the maximum emios channel allocation. 3.5.9 deserial serial peripher al interface module (dspi) mpc5602d devices have two dspi modules. features include: ? full duplex, synchronous transfers ? master or slave operation ? programmable master bit rates ? programmable clock polarity and phase ? end-of-transmission interrupt flag ? programmable transfer baud rate ? programmable data frames from 4 to 16 bits output pulse width modulation trigger opwmt x x x x pulse edge accumulation pea x ? ? ? pulse edge counting pec x ? ? ? quadrature decode qdec x ? ? ? single action input capture saic x x x x single action output compare saoc x x x x table 8. emios configuration channel type maximum number of channels counter / opwm / icoc 1 notes: 1 each channel supports a range of modes incl uding modulus counters, pwm generation, input capture, output compare. 5 o(i)pwm / opwfmb / opwmcb / icoc 2 2 each channel supports a range of modes including pwm generation with dead time, input capture, output compare. 7 o(i)pwm / icoc 3 3 each channel supports a range of modes including pwm generation, input capture, output compare, period and pulse width measurement. 7 opwm / icoc 4 4 each channel supports a range of modes including pwm generation, input capture, output compare. 9 table 7. supported emios channel modes (continued) mode channel type description name counter / opwm / icoc o(i)pwm / opwfmb / opwmcb / icoc o(i)pwm / icoc opwm / icoc
device family overview mpc5602d microcontroller product brief, rev. 3.1 preliminary?subject to change without notice freescale semiconductor 17 ? 6 chip select lines for dspi_0 and 5 for dspi _1, depending on package and pin multiplexing, to enable 64 external devices to be select ed using external muxing from a single dspi ? up to 8 transfer types, indepe ndently configurable for each ds pi using the clock and transfer attributes registers ? chip select strobe available as alternate functi on on one of the chip select pins for deglitching ? fifos for buffering up to 4 transfer s on the transmit and receive side ? general purpose i/o functionality on pins when not used for spi ? queueing operation possible through use of edma ? 32-bit serialization of data enabling virtual gpio ports on two dspi modules 3.5.10 controller area network module (flexcan) mpc5602d devices have one flex can module. features include: ? compliant with can protocol specification, version 2.0b active ? 32 mailboxes ? mailboxes configurable while modul e remains synchronized to can bus ? each mailbox configurable as transmit or receive ? transmit features ? supports configuration of multiple mailboxes to form message queues of scalable depth ? arbitration scheme according to me ssage id or message buffer number ? internal arbitration to guarantee no inner or outer priority inversion ? transmit abort proce dure and notification ? receive features ? 2 mailboxes filtered ? programmable clock source ? system clock ? direct oscillator clock to avoid pll jitter ? listen-only mode capabilities 3.5.11 system clocks and clock generation the following list summarizes the system clock and clock generation on the mpc5602d: ? system clock can be derive d from the following sources ? external crystal oscillator ?fmpll ? 16 mhz fast internal rc oscillator ? programmable output clock di vider of system clock ( ? 1, ? 2, ? 4) ? separate programmable periphe ral bus clock divider ratio ( ? 1, ? 2, ? 4) applied to system clock ? frequency modulated phase-locked loop (fmpll)
mpc5602d microcontroller product brief, rev. 3.1 preliminary?subject to change without notice device family overview freescale semiconductor 18 ? input clock frequency from 4 mhz to 16 mhz ? clock source: external oscillator ? lock detect circuitry conti nuously monitors lock status ? loss of clock (loc) detection fo r reference and feedback clocks ? on-chip loop filter improves electromagnetic in terference performance reduces number of external components required ? on-chip fast external crystal os cillator supporting 4 mhz to 16 mhz ? dedicated 16 mhz fast internal rc oscillator ? used as default clock source out of reset ? provides clock for rapid st artup from low power modes ? provides back-up clock in the event of fm pll or external oscillator clock failure ? offers independent clock source for the watchdog timer ? 5% accuracy over the operating temperature range ? trimming registers to support frequency ad justment with in-appl ication calibration ? dedicated 128 khz slow internal rc oscillator for low power mode operation and self wakeup ? 10% accuracy ? trimming registers to s upport improve accuracy with in-application calibration 3.5.12 system timers 3.5.12.1 introduction the system timers include: ? peripheral interrupt timer (pit ) timers (including adc trigger) ? 1 real-time count er (rtc) timer the pit is an array of timers that can be used to raise interrupts, trigger ctu channels, and adc conversions. the rtc supports wakeup from low power modes or real-t ime clock generation. 3.5.12.2 periodic interrupt timer module (pit) the pit features the following: ? 4 general purpose interrupt timers ? 1 interrupt timers for triggering ad c injected conversions (12-bit adc) ? up to 2 interrupt timers for triggering dma transfers ? 1 interrupt timers for triggering ctu ? 32-bit counter resolution ? clocked by system clock frequency
device family overview mpc5602d microcontroller product brief, rev. 3.1 preliminary?subject to change without notice freescale semiconductor 19 3.5.12.3 real-time counter (rtc) the rtc features the following: ? configurable resolution for different timeout periods ? 1 sec resolution for > 1 hour period ? 1 ms resolution for 2 second period ? selectable clock sources ? 128 khz slow internal rc oscillator ? divided 16 mhz fast internal rc oscillator ? supports continued operation through all resets except por (power-on reset) 3.5.13 system watchdog timer the watchdog on the mpc5602d features the following: ? activation by software or out of reset ? 32-bit modulus counter ? clock source: robust 128 khz slow internal rc oscillator (divisible by 1 to 32) ? supports normal or windowed mode ? configurable response on timeout: reset, in terrupt, or interrupt followed by reset ? reset by writing a software key to memory mapped register ? support for protected access to watchdog control registers with optional soft and hard locks ? soft lock allows temporar y locking of configuration ? once enabled, hard lock prevents any changes until after a reset ? supports halting duri ng low power modes 3.5.14 on-chip voltage regulator (vreg) the on-chip voltage regulator in cludes the following features: ? optional support for internal and external ballast resistor based on power consumption ? regulates 3.3 or 5 v 10% input to generate all internal supplies for internal control ? manages power gating ? low power regulators support operation when in stop and standby modes to minimize power consumption ? fast startup on-chip regulators for rapid exit from low power modes ? low voltage reset supporte d on all internal supplies 3.5.15 analog to digital converter module (adc) the adc features the following: ? one 12-bit adc module supporting s ynchronous conversions on channels
mpc5602d microcontroller product brief, rev. 3.1 preliminary?subject to change without notice device family overview freescale semiconductor 20 ? 0?v dd common mode conversion range ? conversions times of < 2 s available 1 ? up to 33 single ended inputs ch annels, expandable to 61 channels with external multiplexers ? internally multiplexed channels ? up to 33 channels of which 16 high-accuracy ? dedicated result register availabl e for every internally muxed channel ? externally multiplexed channels ? internal control to support generation of external analog multiplexor selection ? 4 internal channels optionally used to s upport externally multiplexed inputs, providing transparent control for additional adc channels ? each of the 4 channels supports up to 8 externally muxed inputs ? individual dedicated result register also avai lable for externally muxed conversion channels ? 3 independently configurable sample and conversion times for high occurrence channels, internally muxed channels and externally muxed channels ? support for one-shot, scan and injection conversion modes ? independently configurable sampling duration for each type of channel ? conversion triggering support ? internal conversion triggering from periodic interrupt time r (pit) or timed i/o module (emios) through cross tr iggering unit (ctu) ? internal conversion triggering from periodic interrupt timer (pit) ? 1 input pin configurable as ex ternal conversion trigger source ? up to 6 configurable analog comp arator channels offering range comparison with triggered alarm ? greater than ?less than ? out of range ? all unused analog pins availa ble as general purpose input pins ? unused 12-bit adc analog pins, with the excepti on of the 16 dedicated high accuracy channels, available as general purpose output pins ? power-down mode ? supports dma transfer of results based on en d of conversion chain or each conversion ? separate dedicated dma request for injection mode 3.5.16 enhanced direct memory access controller (edma) the following summarizes the mpc5602d?s implementation of the edma controller: ? 16 channels to support independent 8-, 16-, or 32-bit single value or block transfers ? support of variable sized queues and circular queues 1. please refer to the data sheet for up- to-date values on current consumption. this value is only estimates and has not been validated.
device family overview mpc5602d microcontroller product brief, rev. 3.1 preliminary?subject to change without notice freescale semiconductor 21 ? source and destination address regi sters are independently configured to post-increment or remain constant ? each transfer is initiated by peripheral, cpu, periodic timer interrupt or edma channel request ? peripheral dma request sources include dspis, 12-bit adc, emios and gpios ? each edma channel able to optionally send interrupt request to cpu on completion of single value or block transfer ? dma transfers possible between system memori es and all accessible me mory mapped locations including peripheral and registers ? programmable dma channel mux allows assignm ent of any dma source to any available dma channel with total of up to 16 potential request sources 3.5.17 cross trigger unit (ctu) the ctu enables the synchronization of adc conversi ons with a timer event. its key features are: ? single cycle delayed trigger output trigged by up to 29 input flags/events connected to different timers in the system ? triggers adc conversions from any emios channel ? triggers adc conversions from one dedicated pit ? maskable interrupt generation whenev er a trigger output is generated ? 1 event configuration register dedicated to e ach timer event allows to define the corresponding adc channel ? acknowledgment signal to emio s/pit for clearing the flag ? synchronization with adc to avoid collision 3.5.18 serial communication interface module (linflex) the linflex on the mpc5602d features the following: ? 3 linflex modules supported ? supports lin master mode, lin slave mode and uart mode ? 1 module supporting lin master and slave m ode; 2 modules support ing lin master mode ? lin state machine compliant to lin 1.3, 2.0 and 2.1 specifications ? handles lin frame transmission and reception without cpu intervention ? lin features ? autonomous lin frame handling ? message buffer to store iden tified and up to 8 data bytes ? supports message length of up to 64 bytes ? detection and flagging of lin errors ? sync field ? delimiter ?id parity
mpc5602d microcontroller product brief, rev. 3.1 preliminary?subject to change without notice device family overview freescale semiconductor 22 ? bit, framing ? checksum and timeout errors ? classic or extended checksum calculation ? configurable break duration of up to 36-bit times ? programmable baud rate prescalers (13-bit mantissa, 4-bit fractional) ? diagnostic features ? loop back ?self test ? lin bus stuck dominant detection ? interrupt driven operation with 16 interrupt sources ? lin slave mode features ? autonomous lin header handling ? autonomous lin response handling ? 16 id filters for discarding irrelevant lin responses ? uart mode ? full-duplex operation ? standard non return-to-zero (nrz) mark/space format ? data buffers with 4-bytes receive, 4-bytes transmit ? configurable word length (8-bit or 9-bit words) ? error detection and flagging ? parity, noise and framing errors ? interrupt driven operation with 4 interrupt sources ? separate transmitter and r eceiver cpu interrupt sources ? 16-bit programmable baud rate modulus counter ; baud rate can be fractioned with 1/16 granularity ? 2 receiver wakeup methods mpc5602d devices include two functi onally different linfle x controller types. th ese are distinguished in the documentation by the abbreviations ?linflex? and ?linflexd?. the letter ?d? indicates that the ?linflexd? unlike the plain ?linflex? supports the dma. the mpc5602d devices combine thes e two types to provid e up to three modules supporting the linflex protocol. the module (instance) num bers and the corresponding functiona l controller type are listed below: ? module 0 ? linflexd ? module 1 ? linflex ? module 2 ? linflex
device family overview mpc5602d microcontroller product brief, rev. 3.1 preliminary?subject to change without notice freescale semiconductor 23 3.5.19 jtag controller (jtagc) jtag features the following: ? jtag low pin count interface (ieee 1 149.1) test access port (tap) interface ? backward compatible to standard jtag ie ee 1149.1-2001 test access port (tap) interface ? supports boundary scan testing ? all jtag pins reusable in application as standard i/os 3.6 packages mpc5602d family members are offered in the following package types: ? 64-pin lqfp, 0.5 mm pitch, 10 mm x 10 mm outline ? 100-pin lqfp, 0.5 mm pitch, 14 mm x 14 mm outline
mpc5602d microcontroller product brief, rev. 3.1 preliminary?subject to change without notice application example freescale semiconductor 24 4 application example the mpc5602d is designed to addre ss central body, vehicle body controll ers, smart junc tion box and front module applications, and to support sensorless motor c ontrol with ripple counting within the vehicle. as shown in the following exampl e, the mcu is central to the applicat ion and provides the flexibility to add or remove peripheral com ponents in a modular design. 4.1 body controller application example body controller modules prim arily control the following: ? comfort features?doors, se ats, interior lighting ? security/access features ?passive entry, immobilizer, tire-pressure monitoring system (tpms) ? lighting?headlights, br ake lights, turn lights ? centralized diagnostic and network management ? vehicle communications network rout ing? controller area network (can) figure 2 shows the mpc5602d used in a t ypical body controller application. figure 2. body controller application example 5 developer environment the mpc5602d mcu family is supporte d by tools and third-party develo pers similar to those supporting freescale mpc5500 products, offering a widespread, es tablished network of tools and software vendors. the following development support is available: ? automotive evaluation boards (evb) feat uring can, lin interfaces, and more can can battery monitoring, digital outputs digital inputs (including adc sci lin ls can body hs can powertrain hs can diagnostic power seat steering column rain sensor and sunroof control lin and misc. sensors input capture signals) rf receiver (eg pwm,gpio) analog inputs diagnostic spi spi can switch panel and digital sensors direct loads (cabin lighting, locks power latch pumps,..) mux advanced corner lighting window lift timed i/o park distance control adc smart power (lighting...) mpc5601/2dx
orderable parts mpc5602d microcontroller product brief, rev. 3.1 preliminary?subject to change without notice freescale semiconductor 25 ? compilers ? debuggers ? jtag and nexus1 interfaces the following software support is available: ? osek solutions is available from multiple third parties ? can and lin drivers ? autosar package 6 orderable parts figure 3. commercial product code structure 7 revision history table 9 summarizes revisions to this document. table 9. document revision history revision date substantive changes 1 11 feb 2009 initial release 2 28 may 2010 updated the entire document 2.1 14 jul 2010 corrected the security classification of this document (is fcp) qualification status power architecture core automotive platform core version flash size (core dependent) product optional fields mpc56 demll example code: 02 temperature spec. package code qualification status m = mc status s = auto qualified p = pc status automotive platform 56 = power architecture in 90 nm core version 0 = e200z0h flash size (z0 core) 1= 128 kb 2 = 256 kb product d = access family optional fields e = data flash (blank if none) r = tape & reel (blank if tray) r temperature spec. c = ?40 to 85 c v = ?40 to 105 c m = ?40 to 125 c package code lh = 64 lqfp ll = 100 lqfp
mpc5602d microcontroller product brief, rev. 3.1 preliminary?subject to change without notice revision history freescale semiconductor 26 3 27 ago 2010 replaced all occurrences of ?e200z0? with ?200z0h? added contents concerning edma and i 2 c blocks in the ?mpc5602d series block summary? table. removed ?current consumption estimates? table removed second level bullet from ?i nterrupt controlle r (intc)? section removed ?flash partitioning? table updated the footnote of ?analog to digital converter module (adc)? section rewrote first bullet within ?cross trigger unit (ctu)? section updated the ?serial communication interface module (linflex)? section removed ?p/i? from the blocks of ?body controller application example? figure removed ?order code? table 3.1 23 feb 2011 deleted the ?freescale confidential proprietary? label (the document is public). table 9. document revision history (continued) revision date substantive changes
how to reach us: home page: www.freescale.com web support: http://www.freescale.com/support usa/europe or locations not listed: freescale semiconductor, inc. technical information center, el516 2100 east elliot road tempe, arizona 85284 1-800-521-6274 or +1-480-768-2130 www.freescale.com/support europe, middle east, and africa: freescale halbleiter deutschland gmbh technical information center schatzbogen 7 81829 muenchen, germany +44 1296 380 456 (english) +46 8 52200080 (english) +49 89 92103 559 (german) +33 1 69 35 48 48 (french) www.freescale.com/support japan: freescale semiconductor japan ltd. headquarters arco tower 15f 1-8-1, shimo-meguro, meguro-ku, tokyo 153-0064 japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com asia/pacific: freescale semiconductor china ltd. exchange building 23f no. 118 jianguo road chaoyang district beijing 100022 china +86 10 5879 8000 support.asia@freescale.com freescale semiconductor literature distribution center 1-800-441-2447 or +1-303-675-2140 fax: +1-303-675-2150 ldcforfreescalesemiconduc tor@hibbertgroup.com information in this document is provided solely to enable system and software implementers to use freescale semiconductor products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does freescale semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters that may be provided in freescale semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals?, must be validated for each customer application by customer?s technical experts. freescale semiconductor does not convey any license under its patent rights nor the rights of others. freescale semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the freescale semiconductor product could create a situation where personal injury or death may occur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indemnify and hold freescale semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part. freescale? and the freescale logo are trademarks of freescale semiconductor, inc. the described product contains a powerpc processor core. the powerpc name is a trademark of ibm corp. and used under license. all other product or service names are the property of their respective owners. ? freescale semiconductor, inc. 2009, 2010. all rights reserved. MPC5602DPB rev. 3.1 02/2011

▲Up To Search▲

Price & Availability of MPC5602DPB

	To Download MPC5602DPB Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .